As circuit density has increased, all or most components of a computer system or other electronic system may be integrated into a single chip to form a system-on-a chip (SOC). The advances in circuit density enable an SOC to include multiple instantiations of a circuit module or hardware module. For example, an SOC for a smart phone may include a quad core central processing unit (CPU), a digital sensing processor (DSP) with four hardware threads, a graphic processing unit (GPU) including four algorithm logic units (ALUs), a plurality of wireless local area network (WLAN) interfaces, a modem having three vector processing engines (VPEs), and multiple L2 cache on-chip memories. As used herein, the terms “core” or “module” are used interchangeably with regard to such multiple instantiations of the same circuit structure.
An SOC will typically be configured with an operating system or some other type of host software application that will select a particular core from a group of the same cores for a particular task. To enable such a selection, each core from a group of identical or substantially identical cores will typically be associated with a serial number or character that serves as identification (ID) or an address of the hardware module. The address may be based upon the geographical location of a hardware core on a die or its manufacturing order (or other parameters). Using the address, the operating system selects a particular hardware module from a group of such hardware modules for a particular task. Ideally, identical hardware modules should exhibit identical characteristics and performance. But with the advances in circuit density, it is common for identical modules such as CPU cores to show considerable variation in their performance and properties. For example, even if cores are directly adjacent to one another on the die, the die itself has semiconductor process variations that cause identical circuits to behave differently. Moreover, the die may have temperature or voltage variations at the different locations for the hardware modules that will also affect their performance. However, present hardware core selection schemes do not account for these individual characteristics.
There is thus a need in the art for a processor architecture that intelligently selects hardware cores to increases performance and lower power consumption.